Networking ASIC Architect
Job Area
Engineering – Hardware
Job Description
In this position, the candidate will need to define the network switching/adapter ASIC chip architecture, lead the performance modeling and system prototype, and coordinate the implementation of the design with the implementation team.
Responsibilities
1. Define the Ethernet network switching/adapter ASIC chip level architecture
2. Discuss with the other architecture team in the ASIC architecture details.
3. Coordinate with and support RTL design and verification teams
4. Coordinate with and support driver development teams.
5. Define the algorithms to be used in the ASIC.
6. Define the ASIC data structures and interface signals.
7. Communicate to the ASIC designer on the architecture design.
Requirements
1. MS in EE or CE with 8+ years of network switching/NIC ASIC design experience
2. Strong background in networking, Ethernet, Ethernet Switching, Data Center Bridging
3. Good understanding of the networking protocols such as Ethernet, MPLS, TCP/IP, UDP and unicast and multi-cast.
4. Knowledge of new/emerging standards VXLAN, VN-Tag and Port Extension Technology
5. Knowledge of hardware virtualization (SR-IOV, VIA)
6. Have good understanding of the ASIC design methodology
7. Knowledge of Fibre Channel, FCoE, iSCSI or InfiniBand is plus
If interested, please just send your resume to;
(Know anyone like this? We pay for referrals)
Contact;
Mark Apton
Senior Recruiter, Human Resources
Futurewei Technologies - US R&D Center
http://www.linkedin.com/in/markapton
E-mail: mark.apton@huawei.com
2330 Central Expressway, Santa Clara, California, 95050
Phone: 408- 330-5338; Fax: 408-330-5089
www.usahuawei.com ($30B.)
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